ArC TWO

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ArC TWO Hardware

ArC TWO Control Panel

ArC TWO

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ArC TWO is a generic microchip characterisation platform, including emerging memory crossbar arrays but also other types of components such as data converters. It features 128× channels, of which 64× are independent source-meter units with full analogue capabilities up to ±20 V, enable work with NT1R crossbar arrays, digital microchips with up to 128 pads and analogue or mixed-signal chips with up to 64 analogue pads. An ArC TWO board includes: a) a straightforward and extendable user interface for quick starting; b) a detachable daughter-board slot allowing for custom PCBs to piggy-back on ArC's infrastructure and c) an open-source API for advanced users.

ArC TWO Control Panel: 0.1.0, or github

ArC TWO Python Bindings: or github

User Manual with UI introduction: [HTML]

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ArC TWO is a fully parallel instrument: this means it is designed to allow concurrent and independent control of its 128× terminals. This enables significant capabilities such as the handling of NT1R crossbar arrays for emerging memory (32× analogue wordlines + 32× analogue bitlines + 32× digital control lines for example) or the characterisation of generic ICs such a data converter chip. The interface is straightforward and extendable, designed to allow non-specialist users to enjoy basic functionality with minimal training and the entire instrument fits on a desktop and can even be easily transported for cross-laboratory experiments.

The current version of ArC TWO inherits all of the functionality present in ArC ONE, allowing I-V measurement, voltage biasing under current compliance and an array of automated tests. However, it also adds significant new functionality such as biasing via fine-grained series resistances (0-1kOhm in 1000 steps), high-speed pulse capability (down to 40 ns) and -of course- fully parallel biasing of complex circuits or arrays.

Similar to ArC ONE, executing a variety of microchip tests becomes trivial via the implementation of automated testing. Moreover, tests can be executed with results displayed in real-time. Finally, we offer a service for developing any testing module that suits your needs, but also developing daughter-boards to host your selection of test chips and/or connectors to other systems such as potentially probe cards. Email us if you have specific needs regarding modules, daughter-boards or probe-cards for more a more detailed discussion.

Technical paper about ArC TWO: P. Foster, J. Huang, et al, "An FPGA-based system for generalised electron devices testing", Sci. Rep., 12, 13912, 2022

Reading Operations

Current Readings:

Accuracy: 1% at >16 nA, 10% at >1.6 nA
Minimum current measurement: ±200 pA
Maximum current measurement: ±10 mA
Current measurement resolution: 2.6 pA
Current measurement time: 1.5 ms

Voltage Readings:

Accuracy: 1% at >20 mV, 10% at >2 mV
Minimum voltage measurement: ±200 μV
Maximum voltage measurement: ±10 V
Voltage measurement resolution: 77 μV
Voltage measurement time: 10 μs (single sample), 320 μs (averaged)

Programming Operations

Maximum bias voltage: ±13.5 V
Bias voltage resolution: 305 μV at ±10 V, 610μ V at ±13.5 V
Bias voltage current limit: 10 mA (200mA across all channels)
Bias voltage slew rate: 400 mV/μs
Arbitrary Pulse generator voltage: ±13.5 V
Arbitrary Pulse generator width: 40 ns - inf
Arbitrary Pulse generator time resolution: 10 ns
Arbitrary Pulse generator current limit: 10 mA

Operation Intervals

Minimum READ → WRITE interval: 20 μs
Minimum WRITE → READ interval: 150 μs

Programmable I/O

64 fully independent SMU channels with pulse generators and access to unified current source
32 digital outputs with arbitrary high/low levels at ±13.5 V
32 digital I/Os with arbitrary high level at 1.8-5.5 V
4 arbitrary supplies at ±13.5 V and ±100 mA

Crossbar management

SMU configuration for up to 32×32 selector enabled crossbar array
With 32NNA68 daughterboard (included as default): (a) Switchable header pin array for access to all channels; (b) 68 pin PLCC socket for packaged samples (up to 1 kbit crossbar arrays)
Optional 32-port SMA array and 12-port BNC array daughterboards for probe interface
Optional 48-pin ZIF DIP socket daughterboard for use in general characterisation tasks with DIP packaged arrays

Expansion capability

132-pin mezzanine connector exposes all analogue and digital pins of ArC TWO for fully customised daughterboards

Software components

Ready to use Python based, open source control panel: ArC TWO Control.
Read Single, Read All or Read Stand Alone capabilities;
Click-to-pulse: apply single voltage pulse optionally followed by a read operation;
Real-time view of resistance evolution, with history of all pulsing operations performed;
Expansion API: Design and develop new experiments as Python modules
Open source Python library (pyarc2) to develop fully customised scripts and programs.
Open source low level API that fully exposes the hardware capabilities down to instruction pipelining for mission critical applications: libarc2.
HDF5-based structured file format, accessible by any software that can handle HDF5 files (bring your own analysis tooling!)
All software available for 64-bit Windows 10+ or Linux (only for glibc-based distributions, glibc ≥ 2.14; musl systems not supported)

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